Class D amplifiers comprise a switching power stage for driving a load. The output signal is a pulse-width modulated (PWM) signal. The output signal is further low-pass filtered at the amplified output and the remaining signal is the analog output signal. A multi-level PWM signal, which represent more accurately the input signal may be used, for reducing the high frequency content, and simplify filtering. For such an amplifier, an output stage that can reproduce multiple output levels may be used. FIG. 1, shows a common way to implement a multi-level switching power-stage, that operates from a single supply voltage. It is implemented by putting multiple half-bridge switching stages in parallel i.e. combinations M1, M3 and Mx, My in FIG. 1. When the parallel stages are driven by appropriate signals and the outputs are summed up, a multi-level PWM output is generated. A three-level switching power stage using this principle is shown in FIG. 1. Z1 and Z2 are inductors, for making an accurate superposition of the output signals from the parallel half-bridge stages.
The three-level switching stage shown in FIG. 1 may generate an output signal with a level equal to ground, half supply voltage Vs or supply voltage Vs. A known circuit for deriving a voltage that equals half of the supply voltage is a capacitive divider as shown in FIG. 2 and also in Bekhout, Marco “Integrated Audio Amplifiers in BCD Technology”, Kluwer Academic Publishers, 1997. If an output voltage V0 is larger then half the supply. Capacitor C2 will be discharged by the load current I1 and the voltage across the capacitor will decrease and hence the output voltage Vo. Capacitor C1 is charged by the load current I1 and the voltage across this capacitor will increase. When the output voltage drops a certain value below half the supply voltage the capacitors are interchanged. The capacitor C1 connected between nodes a and b before interchanging will be connected between nodes c and d afterwards with the positive plate of the capacitor connected to node c. Capacitor C2 connected between nodes c and d will after interchanging be connected between nodes a and b with the positive plate of the capacitor connected to node a. After the interchanging the output voltage is again above half the supply voltage. By repeating the interchanging of the capacitors continuously a voltage equal to half the supply voltage with some ripple is generated.
The circuit also works if only one capacitor is and it is switched as was the case for the situation with two capacitors. During switching the output voltage is not defined. A buffer capacitor can be added to supply the current to the load during switching. Because of the series-parallel connection of C1 and Cb there will be some charge redistribution and the steady-state output will be somewhat lower then half the supply voltage as is shown in FIG. 3. The implementation of this capacitive divider stage is less complex than that shown in FIG. 2 and requires fewer transistors.